FPGA autonomous logic analyzer using innovative BERC filter optimization

In this work is presented a new hardware implementation of a high speed logic analyzer inside FPGA (Field Programmable Gate Array) chips that is fully autonomous by directly driving a VGA compatible computer monitor for multiple signals display. It can be used as a very low cost and real time testing instrument for both external hardware and internal FPGA designs. The implementation is optimized at schematic level by proposing an innovative solution called BERC (Begin-End-Reset-Cell) as hardware digital filter that eliminates any magnitude or equality comparators usually inferred from hardware description languages to decode the counters signals. This new technique is much more efficient because it reduces the combinatorial resources to a minimum, and it can be generalized for all kind of video interfaces.