Adaptive front-end throttling for superscalar processors

To achieve high performance, conventional superscalar processors maintain maximum front-end instruction delivery bandwidth, which is often suboptimal when program behavior and priority metrics change. This paper proposes an adaptive front-end throttling technique that dynamically adjusts the front-end instruction delivery bandwidth as program behavior changes to optimize a target metric, being performance, energy, or an arbitrary trade-off between them. Circuit-level synthesis (45nm FreePDK) and simulation show that adaptive front-end throttling incurs negligible overhead but achieves average improvements of 7%, 28%, 28%, and 32% for performance, energy, energy-delay product, and energy-delay-squared product, respectively, over all benchmarks on an 8-way superscalar processor.