An Interface for Open-Drain Bidirectional Communication in Field Programmable Interconnection Networks

An open-drain interface circuit and a corresponding interconnect topology is proposed to support bidirectional communication in a field programmable interconnection network (FPIN), similar to those implemented in field programmable gate arrays (FPGAs). The proposed interface can interconnect multiple nodes in a FPIN. With that interface, the interconnection network imitates the behavioral of open-drain (or open-collector) buses (e.g., those following the I
²
C protocol). Thus, multiple open-drain I/Os from external integrated circuits (ICs) can be connected together through the FPIN by the proposed interface circuit. The interface that has been fabricated in a 0.13 μm CMOS technology takes 65 μm×22 μm per pin. Test results show that several instances of this interface can be interconnected through the proposed interconnect topology. The topology was implemented and tested combining six open-drain I/Os. The interconnect has propagation delays of approximately 0.26·n+51 ns and 0.26·n+94 ns for rising and falling edge transitions respectively, when each pin has a capacitance of 15 pF, where n is the number of interconnected interfaces. These delays and the propagation delays of the FPIN limit the maximum number of interface circuits that can be interconnected for a given communication speed ( I
²
C fast-mode plus with 3.4 Mbit/s).