FPGA-based Internet Protocol Version 6 router

In this paper, a novel hardware design for an Internet Protocol Version 6 router using field programmable gate arrays is proposed. A dataflow, parallel, pipelined and scalable architecture is presented that has the potential of matching the enormous communication bandwidths of transmission links. A ternary content addressable memory (CAM) in the form of cache is adopted as a routing table search engine. It can offer O(1) search time with just O(N) memory words. Adding a sorting (priority) mechanism by caching the routing table in CAM and using a modified form of sector mapping technique eliminates the slow insertion and deletion times without adding significant additional hardware costs.