VLSI design of a quaternary carry ripple adder

The design of a CMOS quaternary carry ripple adder is presented. The adder uses a single 5-V power supply. Layout and simulations for 4-, 8-, and 16-stage adders were done with MCNC (Microelectric Center of North Carolina) tools for VLSI design. The simulation results are compared with results for equivalent binary adders in terms of speed, chip area, power dissipation, number of transistors, and noise margin. The study indicates a speed advantage for the quaternary adder as the number of stages are increased.<
>