Design of a high gain organic comparator for use in low-cost smart sensor systems

This paper presents novel designs of a 3-stage organic comparator, a key building block of an organic analogue-to-digital converter (ADC), for integration in low-cost smart sensor systems. The designs adopt a pseudo-PMOS configuration so as to allow ease of fabrication of the comparator. DC and transient analysis are carried out using modified silicon models with organic parameters, so as to accommodate the properties of an organic transistor. Two topologies of the comparator designs are simulated, with the aim of enhancing the overall gain. The effect of threshold voltage variation on the outputs of the two designs is also examined. For a variation of 1 V, small shifts in the output voltage of 0.01 V to 0.3 V are observed respectively. Moreover, the DC open loop gain for the two designs are found to range between 45.72 dB to 60.95 dB and 22.97 dB to 54.73 dB for the 1
^st
and 2
^nd
designs respectively. The latter gains of both designs are currently the highest reported in the literature for an organic comparator. In addition, the propagation delay and resolution also varied depending on the design, such that values of 0.05 ms to 0.16 ms and 0.3 V to 0.6 V were attained for the 1
^st
design respectively, and 0.12 ms to 0.18 ms and 0.08 V to 0.8 V were attained for the 2
^nd
design. Overall comparison of the two designs revealed that additional gain stages results in larger bandwidth and better resolution however it also reduces the output voltage swings, gain and operational speed. For use in sensor applications, particularly artificial skins and e-textile clothing, the output specifications of the 1
^st
design are considered adequate, despite the trade-offs on the bandwidth and resolution.