A 25GS/s 6b TI binary search ADC with soft-decision selection in 65nm CMOS

A 25GS/s 8-way time-interleaved binary search ADC employs a novel soft-decision selection algorithm to improve metastability tolerance and relax T/H settling requirements. The T/H design is further relaxed with reduced loading from a new shared-input three comparator structure. Fabricated in GP 65nm CMOS, the ADC achieves 4.62-bits ENOB at Nyquist and 143 fJ/conv.-step FOM, while consuming 88mW and occupying 0.24mm
²
core ADC area.