FPGA based accelerator for visual features detection

In the context of obstacle detection and tracking for a vision-based ADAS (Advanced Driver Assistance System), one mandatory task is vehicle localization. Vision-based SLAM (Simultaneous Localization and Mapping) proposes to solve this problem by combining the estimation of the vehicle state (localisation : position and orientation) and an incremental modelling of the environment using a perception module (feature detection and matching) in images acquired using one camera or more. Such a perception module requires an important computational load that highly affects the latency and the throughput of the system. Our goal is to implement the SLAM functionality on a low power consumption mixed hardware and software architecture (using a co-design approach) based on a Xilinx Zynq FPGA. This device includes logic cells that allows to speed-up the perception tasks to meet the real-time constraint of an ADAS. In this paper, we present the implementation of two hardware components : a FAST (Features from Accelerated Segment Test) features detector and a parametrizable corner refinement module (Non Maxima Suppression - NMS).