Sub-threshold CMOS circuits reliability assessment using simulated fault injection based on simulator commands

Lowering the supply voltage below the threshold voltage of the transistors brings important benefits regarding the power consumption. However, the main issue of sub-threshold CMOS circuits is the abrupt reliability decrease. This paper proposes a simulated fault injection approach for reliability assessment of gate-level designs supplied at low voltages. The proposed method uses previously determined probabilities of failure of sub-threshold logic gates in order to perform fault injection campaigns based on simulator commands and scripts for several types of adders. The overhead of this method is 6x-30x with respect to the fault-free circuit simulation time. We have validated our technique's accuracy by comparing the results with those of equivalent fault injection methodologies, based on HDL code alteration.