RTL power management

Integrated circuit (IC) designers who believe their competence is in developing the architecture, and not the implementation, are looking to register transfer level (RTL) sign-off as a means of getting system-on-a-chip (SOC) ICs to market quickly. In order to create complex SOC designs with strict performance, power, and cost constraints, designers must utilize high-level floorplanning, timing analysis, and power estimation tools to achieve their goals. This paper shows how high-level power estimation and analysis tools help SOC designers reduce packaging costs, improve reliability, and increase battery life.