Electro-less barrier/seed formation in high aspect ratio via

This paper reports on the results of applying an electroless (Eless) plating technique to the deposition of barrier and seed layers in high aspect ratio through-silicon vias (TSVs) and its potential for reducing costs, improving performance, and raising productivity in 3D Integration. The newly developed technology is applicable not only to barrier/seed deposition on TEOS insulation film but also to the uniform deposition of a seed layer on conventional vacuum-deposited barrier layers (such as PVD-Ta). The application of Eless technology can also reduce the occurrence of voids at the bottom of vias that easily occur in Cu electroplating, even when using thin-film seed layers (under 100 nm), which means that improved productivity and reduced process costs can also be expected.