OASIS/sup R/ Application to Re-Synthesis of FPGA Designs as Standard Cell ASICs

This paper presents the ongoing work on the standard cell-based silicon compiler OASIS. A recent extension of the OASIS' capabilities permits the designer to migrate FPGA designs into standard cell technology. Performing FPGA re-synthesis part of OASIS on real-life designs reinforces the advantages of design capture on algorithmic level over the most commonly used schematic capture design entity.