Simulating Large Systems Using Ldvsim

System designs tare becoming increasingly complex, and simulators must keep pace with their size and complexity. To be effective, a simulator must be fast, user oriented and integrated in the design environment. Speed is possible with the use of abstraction or parallel computation. However, an important feature not considered essential in many simulators is how well the user can interact with the simulator to do the many jobs required of simulation: architectural design, timing verification, protocol testing, and verification. This paper explores issues involved in using a simulator in the design and verification of large systems. We argue that humans are unable to handle the volume of data generated by today's simulators and that new techniques such as assertion testing, alternative data representations, interactive debuggers, and mixed level simulation for verification are necessary.