System-level chip/package co-design for multi-core processors implemented with power-gating technique

Based on a system-level design methodology and a modified power delivery network model, optimization and benchmarking are performed for a processor implemented with the power-gating technique under various package configurations. Optimal widths of the sleep transistors are obtained based on how frequently the processors need to switch between active and idle state. Up to 75% of the energy-delay product saving is observed for the processors using power-gating technique with a low switching frequency. Additionally, the optimal position of the decap insertion is demonstrated to be application dependent.