Switched-capacitor interpolator for direct-digital frequency synthesizers

Direct Digital Frequency Synthesis (DDFS) is an attractive alternative to PLL-based synthesizer architectures, mainly due to a better frequency agility and inferior phase noise. For current technologies such synthesizer architectures typically operate below 100 MHz due to power dissipation constraints and speed limitations. In this paper we propose an alternative architecture that allows a practical speed improvement of DDFS circuits. This consists of using a switched-capacitor (SC) interpolator inserted between the digital-to-analog converter (DAC) and the continuous-time output filter and which allows a relaxation of both the filter selectivity requirements as well as the DAC clock frequency. By choosing an optimum ladder-based architecture for the implementation of such interpolator, the opamps can be designed to settle at the lower input frequency, and thus reducing their own speed and power dissipation requirements, while maintaining low amplitude response variability against component errors.