On the testing of hazard activated open defects

Open defects in CMOS circuits can cause a gate output to go into a high impedance, or “floating” mode, for some input patterns. Since such defects display (large) delay fault behavior, they are commonly assumed to be covered during structural testing by scan based TDF timing tests. TDF tests are generally applied in the launch-on-capture (LOC) scan test mode to avoid “overtesting” the circuit timing from non-functional launch states; also many designs do not support a high speed scan enable to allow at-speed launch-on-shift (LOS) timing tests. Unfortunately, launching timing tests from functional states alone, or even LOC states (which are a superset of functional states), is not sufficient to screen all open defects capable of generating erroneous circuit outputs. CMOS circuits experience a large number of hazards during switching transitions, which result in many more transient logic levels at internal circuit nodes than those predicted by steady state analysis from functional states. Such hazards can activate open defects by precharging a faulty gate output to an incorrect value which is then locked in once the inputs stabilize with the gate output in a high impedance state due to the open. Consequently, many open defects that are commonly assumed to be functionally redundant based on steady state analysis, can in fact be activated in operation and cause circuit failure. These must be targeted during manufacturing tests. In this paper we present a deterministic methodology for targeting hazard activated open defects using not only LOC and LOS tests, but also a new DFT approach that further increases the available test launch states to achieve high coverage. We further show that virtually all of the remaining undetected opens are in fact truly redundant, and do not pose a threat even in the presence of hazards.