A novel approach for power-gating technique with Improved Efficient Charge Recovery Logic

In this paper, a novel approach for power gating technique with Improved Efficient Charge Recovery Logic (IECRL) introduced. An Asynchronous Fine-Grain Power-Gated Logic Technique (AFPLT) developed by Improved Efficient Charge Recovery Logic, which gives logic function to the next succeeding stage. In the AFPLT circuit, IECRL gates acquires power from hand shake controller and become active only when performing required executions. In active mode the leakage currents are suppressed by providing infinite resistance path through the NMOS transistor in pull-up network. In in-active mode IECRL gates are not taken any amount of power, this gives negligible leakage power dissipation. Its maximum power saving against ECRL is up to 82.88% at 100 MHZ input data rate. Similarly the power saving against static CMOS logic is up to 92.68% at 100 MHZ. In AFPLT circuit handshake controller is used to provide power to the IECRL gate and which performs the hand shaking with the neighboring stages. In order to reduce the energy dissipation, the PCR mechanism is used in AFPLT pipeline structure. PCR mechanism is used to transfer the charge of discharging phase of IECRL gate to evaluate phase of the another IECRL gate. Early discharging of IECRL gate can be provided by enhanced C-element called C∗-element.