A low power, high performance, 960 macrocell, SRAM based complex PLD

The design, process features and performance of a 960 macrocell, low power, high density complex programmable logic device (CPLD) is presented. It is fabricated on a 0.35 /spl mu/m, five layer metal, CMOS process which permits this 8.5 million transistor design to fit on a 140 mm/sup 2/ die, dissipate only 330 /spl mu/W of static power at a supply voltage of 3.3 V, and allow system operation of up to 225 MHz.