Hierarchical Verification Framework for Samsung Reconfigurable Processor Video System

The Samsung reconfigurable processor (SRP) is developed to accelerate multimedia applications such as video decoding, audio decoding, and image processing. Owing to coarse-grained reconfigurable array (CGRA) acceleration via software (SW) pipelining and application-specific intrinsic instructions, SRP outperforms other digital signal processors (DSPs) in these application domains. In addition, recent video systems include not only the SRP core but also hardware (HW) accelerators, coupled with demand for better performance. Consequently, the system becomes very complex. and the difficulty of debugging the system increases. Here we propose a hierarchical verification framework for the SRP video system. This approach, coupled with a proper verification plan, not only boosts the verification time for various aspects of the video system (e.g., CGRA specific features), but also helps to achieve verification closure without any verification holes.