A Low-Cost and High-Performance Embedded System Architecture and an Evaluation Methodology

A reduced interface and high performanceembedded system architecture (MSBUS) is proposed in thispaper. The control bus is low-cost and low-power, whereas thedata bus is high-bandwidth and high-speed especially. Inaddition, a Universal Verification Methodology (UVM)-basedperformance evaluation methodology is proposed to estimate thehardware structures. In order to evaluate the bus performance, AHB, AXI and MSBUS DMA are implemented as a case study. The experimental results show that MSBUS DMA uses the leasthardware resources, reduces energy consumption to a half ofAHB and AXI in the block transfer mode, and achieves 3.3 timesand 1.6 times valid bandwidth of AHB and AXI respectively. Moreover, the proposed evaluation methodology is effectivelyused with sufficient accuracy.