Enhanced high speed performance from HDI thin film multichip modules

Summary form only given. A novel packaging technology, ideal for CMOS multichip modules, is described. Thin-film metal and polymer dielectric are used to fabricate five aluminum metal layer structures with 25- mu m-wide, 5- mu m-thick traces, and 11- mu m-thick dielectric layers. The polyimide has a dielectric constant of 3.4 and a dissipation factor of 0.003. A proprietary process is used to generate 35- mu m-wide vias to connect adjacent metal layers electrically. The typical via resistance is 10 m Omega . Vias are staggered, rather than stacked. Typically the bottom layer is a power plane, followed by a ground plane, with 'x' and 'y' orthogonal signal layers and a pad layer on top. Top surface metallization can be gold, aluminum, or solder. With this configuration, good electrical performance is obtained and (HDI) interconnection high-density is possible. The maximum density possible using the current 75- mu m routing pitch is 666 in. of trace per square inch of board. Multichip modules have been fabricated for applications ranging from 2 to 35 ICs, plus associated capacitors and resistors.<
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