Analysis of current conveyor non-idealities for implementation as integrator in delta sigma modulators

This paper analyses the non-idealities of a second generation current conveyor (CCII) in advanced CMOS technologies. Primary sources of errors in the CCII are identified and their effects are analyzed with respect to its application as an integrator for delta sigma modulators. An improved CCII integrator architecture and a robust calibration algorithm are proposed to negate the CCII errors. The proposed integrator is used in the design of a 4
^th
order CCII based delta sigma modulator, simulation results of which reveal the advantages of proposed solution. The modulator designed in a 1V/90nm technology has a 78/70/46 dB DR and 77/69/45 dB SNDR for bandwidths of 2/4/10 MHz and clock frequency of 160 MHz respectively.