High-voltage tolerant circuit design for fully CMOS compatible multiple-time programmable memories

A fully CMOS compatible embedded multiple-time programmable (MTP) memory system using the standard TSMC 0.35 μm CMOS process is presented. The memory cells and the control circuits without extra processing steps do not violate design/electrical rules. By employing the high-voltage tolerant circuit design techniques with the current sense amplifiers, the simulation and measurement results reveal the random access time reaches 11 ns and 13 ns, respectively, after program. It is a cost-effective solution to have CMOS compatible embedded non-volatile memory systems for systems-on-chip (SOC) applications.