Test scheduling using Ant Colony Optimization for 3D integrated circuits

Cost of test scheduling for the 3D integrated circuits (IC) test is increased compared to the 2D IC due to the constraint factors such as the width of Test Access Mechanism (TAM), the number of Through Silicon Via (TSVs), thermal constraint, and test pin count constraint. In this paper, a low cost test scheduling mechanism using Ant Colony Algorithm (ACO) for the 3D IC is proposed. The experimental results using simulation demonstrate that the proposed algorithm has an effective solution for the 3D IC test scheduling.