FPGA implementation of SVPWM control technique for three phase induction motor drive using fixed point realization

The Space Vector Modulation technique is an important PWM generation technique for three phase voltage source inverter in order to generate PWM signals for controlling various AC Motors. In such applications generation of PWM signal, dead time and other computational task requires high sampling rate for wide bandwidth performance. This work focuses on the design of low power and high performance VHDL based SVPWM controller for three phase Induction Motor drive on FPGA. The integer realization of software part results in large number of subroutines thus utilizing large hardware resources on FPGA board leading to more power consumption. Also due to large code density the computational time is more. In this work the software part is implemented with proposed fixed point realization which increases the accuracy, also since there are no subroutines it reduces total area on FPGA board. The code density is less, thereby decreasing computational time and power consumption. The simulation results for SVPWM generated signal are presented in this work. To prove the effectiveness of the proposed method the hardware utilization's by the proposed method are compared with integer realization.