Design of Gate-All-Around Silicon MOSFETs for 6-T SRAM Area Efficiency and Yield

Gate-all-around (GAA) MOSFETs relevant for the 11.9-nm CMOS technology node are optimized with device dimensions following the scale length rule. Variability in transistor performance due to systematic and random variations is estimated with the aid of TCAD 3-D device simulations, for these well-tempered GAA structures. The tradeoff between read stability and write-ability of 6-T static RAM cell designs implemented with GAA MOSFETs with either square or rectangular nanowire channel regions is then investigated, and a calibrated transistor
\({\boldsymbol {{I}}}\)
–
\({\boldsymbol {{V}}}\)
compact model is used to estimate cell yield. The results indicate that a rectangular (thin and wide) channel design achieves the optimal balance between the read yield and write yield and hence provides for the lowest minimum cell operating voltage, estimated to be
\(\sim 0.45\)
V, as well as smaller cell area.