Reciprocal Unit Based on Vedic Mathematics for Signal Processing Applications

Vedic mathematics, is an ancient methodology, has a unique mathematical computation technique based on 16 sutras (formulae). High speed reciprocal unit based on such ancient mathematics is reported in this paper. Implementation methodology was adopted through sahayaks (auxiliary fraction) taken from such ancient mathematics and prototype was designed for practical signal processing applications. On account of the Vedic formulae, reciprocal approximation of a numbers is generated in fewer steps compared to Newton-Raphson's iteration based implementation with appreciable error in accuracy (~0.09%), offer high speed operation. The functionality of the algorithm was checked, and performance parameters like propagation delay, dynamic switching power consumption were calculated through spice spectre using 90nm CMOS technology. The propagation delay of the resulting 5-digit reciprocal unit was only ~3.57uS and consumes ~30.8mW power. The implementation methodology offered substantial reduction of propagation delay, and dynamic switching power consumption from earlier reported Newton-Raphson (NR) based implementation.