A Novel and Unified Digital IC Design and Automation Methodology with Reduced NRE Cost and Time-to-Market

Conventional digital IC computer-aided design (CAD) and automation flow incorporates hierarchical methodology following the Gajski Chart. Such methodology uses separate front end and backend CAD tools in complex and incremental steps, incurring increased design time and higher non-recurring engineering (NRE) costs. In this paper, we propose a novel and unified methodology merging the front end and backend without requiring the front end CAD tool usage. Moreover, the complexity of hierarchical design steps is drastically reduced by mapping the input register-transfer level (RTL) description directly to their corresponding physical designs, derived using the existing CAD tools and stored in pre-computed technology libraries. To reduce the size and storage of these libraries, negation-permutation-negation (NPN) classes have been used throughout. As a result, our proposed methodology offers advantages in terms of significantly reduced NRE costs and time-to-market. To demonstrate these advantages, extensive case studies have been carried out using benchmark circuits. Our experimental results and analysis show that these advantages achieved without limiting our methodology to number of input variables in a function using precomputed technology libraries with 1030 circuits only.