7-nm FinFET CMOS Design Enabled by Stress Engineering Using Si, Ge, and Sn

Bandgap and stress engineering using group IV materials-Si, Ge, and Sn, and their alloys are employed to design a FinFET-based CMOS solution for the 7-nm technology node and beyond. A detailed simulation study evaluating the performance of the proposed design is presented. Through the use of a common strain-relaxed buffer layer for p- and n-channel MOSFETs and a careful selection of source/drain stressor materials, the CMOS design is shown to achieve performance benefits over strained Si, meet the I
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requirements, and provide a path for continued technology scaling.