Automated BIST for regular structures embedded in ASIC devices

Testing complex very large-scale integrated (VLSI) circuits is increasingly difficult. It is almost impossible to achieve high fault coverages without using design for testability (DFT) approaches. In one of the most promising DFT approaches, the complex VLSI circuit is divided into various structural modules, and an appropriate built-in self-test (BIST) scheme for each module is then implemented. This approach also provides a path to board- and system-level test. This paper presents a general procedure to implement BIST for a specific set of modules, i.e., embedded regular structures such as static random-access memory (SRAM), read-only memory (ROM), and register files. We will show that fault coverages achieved with this procedure are greater than 99 percent, because the deterministic BIST algorithms and output-data compaction techniques adopted are structure-specific. Moreover, fault simulations are not needed because the fault coverages are analytically determined by an algorithmic approach. The general procedure presented here results in an automated BIST implementation. An illustration of such a procedure is presented through the BIST register file example.