Design of 2×VDD logic gates with only 1×VDD devices in nanoscale CMOS technology

The novel 2×V
_DD
NOT, NAND, and NOR logic gates have been designed and implemented in a nanoscale CMOS process with only 1×V
_DD
devices. With the proposed dynamic source bias technique, the logic gates can be designed to have 2×V
_DD
tolerant capability. Thus, the new 2×V
_DD
logic gates can be operated under 2×V
_DD
voltage environment without suffering the gate-oxide reliability issue.