Revisiting the silicon-lattice in the high-density 3D-LSIs — In the perspective of device reliability

The dependence of device reliability on the lattice perfectness of the active silicon in the high-density 3D-LSIs containing through-silicon via (TSV) and micro-bump (μ-bump) is extensively investigated using hard X rays at SPring8. The reciprocal lattice space (RLS) data revealed that the Si-lattice structure is highly deteriorated owing to the thermo-mechanical (TM) stress exerted by Cu-TSVs and CuSn μ-bumps, and the local mechanical (LM) stress caused by local deformation. The TM stress caused by 20 μm-width Cu-TSV at 300 °C has introduced (i) ~3 degrees of lattice-tilt (mis-orientation) and (ii) ~8.3 % reduction in lattice space (d) values for Si(004) lattice planes in the 3D-LSI chip. This d change has caused a maximum strain of -0.96 %, which corresponds to -1300 MPa of compressive stress. After the curing, the locally deformed upper thin LSI die with 30 μm thickness witnessed as high as 4.9 % increase in d value, and the lattice tilt amount to 0.65 degree. More importantly, the lower 300 μm-thick active/passive interposer has also experienced the lattice tilt and the change in d to the magnitude of around 0.2 degree and 0.4 %, respectively. We have also observed a degradation in the retention time for the stacked memory chip with a decrease in the chip thickness. The median retention time in the 30 μm-thick DRAM-chip was reduced to one-half the retention period for the 100 μm-thick DRAM chip. We explain this phenomenon by deteriorated Young's modulus values and distorted lattice structures in the ultra-thin LSI Si chip. We were able to minimize the TM stress in the active Si to one-third from that of the initial value by sandwiching an organic stress-absorbing polymer between the dielectric layer and the Ta barrier layer, and the polymer is stable up to 400°C.