A study of ESD-induced latent damage in CMOS integrated circuits

ESD-induced latent damage in CMOS integrated circuits has been thoroughly investigated after cumulative low-level ESD stress. A study of the latent damage for transistors at the package level has been performed with various kinds of ESD stress modes. The impact of latent damage on circuit performance degradation was also evaluated using a 64 Mb DRAM chip as a DUT.