A 32/spl times/32-b adiabatic register file with supply clock generator

A 32/spl times/32-b adiabatic register file with one read port and one write port is designed. A four-phase clock generator is also designed to provide supply clocks for adiabatic circuits. All the word line and bit line charge on the capacitive interconnections is recovered to save energy. Adiabatic circuits are based on efficient charge recovery logic (ECRL) and are integrated using 0.8 /spl mu/m complimentary metal-oxide-semiconductor (CMOS) technology. Measurement results show that power consumption of the core is significantly reduced by a factor of up to 3.5 compared with a conventional circuit.