A generic scaleable image processing architecture for real-time military applications

This paper presents the design of a general-purpose, real-time image processing architecture, required for developing proof of principle demonstrations of military image processing applications. The main requirements of the architecture are to provide a scaleable, modular parallel processing framework, with very high bandwidth (at least 64 MByte s/sup -1/) point to point interprocessor communications. The architecture is heterogeneous, and a particular combination of processors may be chosen according to the application. A strong emphasis has been placed on the use of open standards, both for the hardware and software, and, where possible, COTS products are used.