A prototype test system for massively-parallel electrical testing of high density interconnect substrates

Summary form only given. Conventional tests for electrical interconnections in high density substrates utilize one or more moving probes to measure net capacitance and/or resistance between nodes. These methods provide adequate fault coverage for "opens" and "shorts". However, large area substrates containing thousands of nets require excessive time for mechanical positioning of the probe(s). The researchers propose an alternative method whereby all exposed nodes sue simultaneously connected to a high channel count test system. The network is then electrically tested in a single step. During the test, each net is excited through one node with a unique digital "signature" made up of 16 to 32 serial bits. Other nodes connected to these nets are monitored by the test system. All monitored signatures should match with the expected signatures in a fault-free substrate. A faulty substrate will exhibit one or more incorrect signatures. A prototype test system that implements the digital test function is described in this work. The system is constructed using low-cost Field Programmable Gate Arrays (FPGAs), so that expansion to large channel count is economically feasible. Both an immediate Pass/Fail response and diagnostic information is obtained in a fraction of a second. The diagnostic data may optionally be analyzed if fault classification is desired.