A new decoding solution for the asynchronous sigma delta modulator

A new type of low power decoding circuit for asynchronous sigma delta modulators is presented. The circuit implements a special coarse-fine time-to-digital converter to quantize the square wave produced by asynchronous sigma delta modulators, and converts the duty cycle to a digital output. The time-to-digital converter operates asynchronously by utilizing vernier delay lines. The purpose of this circuit is to achieve a high resolution with a low frequency sampling clock, which is suitable for the ultra-low power applications. The proposed circuit is designed in 0.35um. Spectre simulations, show an 11-bit resolution is realized with 0.06LSB integral non-linearity and 0.04LSB differential non-linearity. The simulated power consumption is below16uW from a dual 0.6 V supply voltage.