High-speed area-efficient inner-product processor

In this paper, a novel technique for the design of a high-speed word-level two's complement fixed-point inner-product processor is described. The new scheme offers a highly regular structure ideally suited for VLSI implementation. A comparison in terms of speed and area between the proposed scheme and two other inner-product processors is presented. A reduction in the computation time ranging from 20% to 50% compared with other schemes has been achieved using the proposed processor, without a significant increase in the required area.