Worst-case test vectors for functional failure induced by total dose in CMOS microcircuits with transmission gates

Fault models for total-dose induced functional failure in CMOS microcircuits containing transmission gates have been developed for the automatic generation of worst-case test vectors. We use the circuits in the CMOSN Cell Library. This analysis is supported by SPICE simulation that utilizes experimentally extracted transistor parameters. We have also used our analysis to interpret data from a previous total-dose testing of a test chip designed using the CMOSN Cell Library and fabricated using 1 /spl mu/ technology.