Layout-induced stress effects in 14nm & 10nm FinFETs and their impact on performance

The ever increasing stress engineering raises a major concern of strong layout-dependent effects (LDE) in the advanced technology nodes. We report on the dependency of SiGe S/D and STI induced stress on fin length, position of the gate along the fin and fin to fin distances. The efficiency of epitaxial S/D SiGe stressors is reduced when the fin length is decreased and strongly degraded for fins with a single gate regardless of the SiGe depth, resulting in up to 21% performance degradation at ring oscillator level. Although tensile STI improves the NFETs mobility, the use of compressive STI guarantees a constant mobility ratio and limits the performance variation with layout.