Signal integrity characterization of high-speed I/O in 3D chip-package system

This paper presents signal integrity characterization of 3D TSVs and interconnect using high-speed I/O in a 3D chip-package system. The authors designed and fabricated a Gunning Transceiver Logic (GTL) I/O Test IC using Tezzaron 3D CMOS 150um technology. The test IC has two different tiers which are labeled top and bottom. GTL I/O is placed on each tier to evaluate the TSV and interconnect signal integrity characterization with IGbps data signals. In order to characterize the interconnect in chip-package system, the test ICs were ball-bonded on to a custom FR-4 board designed for measuring high speed transients. Comparison measurements between on-chip and off-chip signals were performed. Also, the GTL I/O drivers switching was enabled at different tiers with a control signal. In addition, specific data patterns are utilized to characterize lSI (Inter-Symbol Interference) from different tiers.