Full wafer nanotopography analysis on rough surfaces using stitched white light interferometry images

Feature sizes of transistors manufactured on silicon wafers in high volume reached 22 nm and will further decrease in the future. Superior wafer surface quality is mandatory to produce such small feature sizes. One relevant quality parameter is the nanotopography of the wafers surface. Applying dedicated state-of-the-art metrology systems, nanotopography is characterized end-of-line of wafer manufacturing on wafers with specular reflectance. In order to continuously improve wafer quality and identify nanotopography related features early, a measurement system capable of characterizing rough wafer surfaces is required. This paper presents a NT analysis approach using a white light interferometer (WLI) with a field of view of 85 × 85 mm
²
. An optimized stitching algorithm merges 16 individual WLI measurements to a height map of an entire 300 mm wafer. Nanotopography can be extracted at wafer edge exclusion below 1 mm by applying flexible Gaussian high-pass filters. A mathematical analysis of nanotopography characteristics according to SEMI M43 is implemented. Gauge repeatability and reproducibility studies provided standard deviations of less than 1 nm on wafer surfaces as-ground by using threshold height analysis (THA). This proves the measurement system's capability for nanotopography analysis at early states of wafer manufacturing, which in turn can support improving wafer surface quality.