Power efficient realtime super resolution by virtual pipeline technique on a server with manycore coprocessors

Super Resolution image processing (SR) is a heavy task for a today's mid-range Xeon server. To accelerate SR, we utilize a server system with manycore coprocessor, Intel Xeon Phi coprocessor. Function offload model is a usual execution model for those systems. However it is difficult for SR to increase utilization of both host processors and coprocessors by the model. We propose a virtual pipeline model which can fully utilize both processors. Experimental results show that our SR improves performance 3.3 times and performance/watt 1.5 times. Our SR achieves 30 frames per sec from SD to HD.