A Novel Modulo $2^{n}-2^{k}-1$ Adder for Residue Number System

Modular adder is one of the key components for the application of residue number system (RNS). Moduli set with the form of 2
ⁿ
-2
^k
-1 (1 ≤ k ≤ n-2) can offer excellent balance among the RNS channels for multi-channels RNS processing. In this paper, a novel algorithm and its VLSI implementation structure are proposed for modulo 2
ⁿ
-2
^k
-1 adder. In the proposed algorithm, parallel prefix operation and carry correction techniques are adopted to eliminate the re-computation of carries. Any existing parallel prefix structure can be used in the proposed structure. Thus, we can get flexible tradeoff between area and delay with the proposed structure. Compared with same type modular adder with traditional structures, the proposed modulo 2
ⁿ
-2
^k
-1 adder offers better performance in delay and area.