FPGA implementation of Low Power High Speed square root circuits

We present an efficient methodology for square root calculation using non-restoring SQUARE ROOT algorithm. The main principle of the proposed method is similar with conventional non-restoring algorithm, except that it eliminates the need for previous quotient in its final iteration. To reduce gate count we have proposed two area efficient subtract units and used in our proposed design. As an enhancement to our work we evaluated the design by eliminating the need for calculation of partial remainder in the final iteration. The proposed design and its enhanced version are designed using VHDL and simulated using Synopsys design compiler. Experimental results demonstrates better performance of our proposed architecture compared with the prior art in terms of area, power and delay.