Embedded tutorial - Emerging memory technologies: What it means for computer system designers

Summary form only given. As conventional memory technologies such as DRAM run into the scaling wall, architects and system designers are forced to look at alternative technologies for building future computer systems. Several emerging Non-Volatile Memory (NVM) technologies such as PCM, STT-RAM, and Memristors have the potential to boost memory capacity in a scalable and power-efficient manner. However, these technologies are not drop-in replacements and will require novel solutions to enable their deployment. Even the prime candidates among these technologies have their own set of challenges such as higher read latency (than DRAM), much higher write latency, and limited write endurance. In this talk, I will discuss some of our recent work that addresses these challenges. Our first solution is hybrid memory system that combines emerging memory technologies with a small DRAM buffer, thereby obtaining the latency of DRAM in the common case, and the higher capacity of emerging technologies. Such a hybrid memory system allows combining technologies that have latency higher than DRAM without having significant impact on read latency. Second, we target the problem of limited write endurance, which is common to many of the emerging memory technologies. This problem is exacerbated by non-uniformity in write traffic to memory, causing frequently written lines to fail much earlier than others thereby reducing system lifetime significantly. Unfortunately, existing wear-leveling techniques require large storage tables and indirection, resulting insignificant area and latency overheads. We propose Start-Gap, a simple and effective wear-leveling technique that incurs an overhead of only few bytes and still provides lifetime close to ideal wear leveling. Finally, I will discuss the performance impact of high write latency, as most of the emerging memory technologies tend to have write latency much higher than the read latency. While a higher write latency can typically be tolerated using buffers, once the write request is scheduled for service to a bank, it can still cause increased latency for later arriving read requests to the same bank. To avoid this latency penalty caused by contention from slow write operations, we propose write cancellation and write pausing as a means to tolerate slow writes.