Reliable Operation of SiC JFET Subjected to Over 2.4 Million 1200-V/115-A Hard Switching Events at 150 $^{\circ}\hbox{C}$

A requirement for the commercialization of power SiC transistors is their long-term reliable operation under hard switching conditions and high temperatures encountered in the field. Normally ON 1200-V vertical-channel implanted-gate SiC JFETs, designed for high-power bidirectional (four-quadrant) solid-state circuit breaker applications, were repetitively pulsed hard switched at 150
$^{\circ}\hbox{C}$
from a 1200-V blocking state to an on-state current of 115 A, which is in excess of 13 times the JFET's 250-
$\hbox{W}/\hbox{cm}^{2}$
rated current at 150
$^{\circ}\hbox{C}$
. The JFETs were fabricated in seven photolithographic levels with a single masked ion implantation forming the
$\hbox{p}^{+}$
gates and guard rings and with no epitaxial regrowth. The pulsed testing was performed using a low-inductance
$RLC$
circuit. In this circuit, the energy initially stored in a capacitor is discharged in a load resistor through the JFET under test. The JFET hard switch stressing included over 2.4 million 1200-V/115-A hard switch events at 150
$^{\circ}\hbox{C}$
and at a repetition rate of 10 Hz. The peak energies and powers dissipated by the JFET at each hard switch event were 73.2 mJ and 68.2 kW, respectively. The current rise rate was 166
$\hbox{A}/\mu\hbox{s}$
, and the pulse FWHM was 1.8
$\mu\hbox{s}$
. After over 2.4 million hard switch events at 150
$^{\circ}\hbox{C}$
, the JFET blocking voltage characteristics remained unchanged while the on-state current conduction slightly improved, which indicate reliable operation.