Spur suppression in frequency synthesizer using switched capacitor array

In this paper we propose a PLL based frequency synthesizer architecture having low spur. Using an array of switched capacitors and a delay locked loop (DLL), a periodic charge distribution technique to suppress reference spur in the PLL has been adopted. The DLL provides the equispaced M instances at which the capacitor array distributes the charge. For the validation of the concept, an integer-N frequency synthesizer with four times repetition of ripples for 916 MHz output frequency and 2 MHz input reference frequency, has been designed in 180 nm CMOS technology. Cadence Spectre simulation shows output spur improvement, with respect to a conventional architecture, of about 59, 75 and 65 dB respectively at 2, 4, 6 MHz offset frequencies while the spur at 8 MHz offset remains unchanged.