Minimization of Trojan footprint by reducing Delay/Area impact

Due to the globalization and capital costs of building and maintaining fabrication facilities, the number of fabs is shrinking every day and more vendors outsource the fabrication process to offshore fabrication facilities. Using such facilities makes the integrated circuits vulnerable to malicious alterations. These alterations are more commonly known as hardware Trojans and are usually created by insertion of additional logic circuitry. In this paper we propose two types of Trojans that we practically generated and explained how we potentially hide them from verification tools and trig them automatically. The minimal performance/area impact of our Trojans is through keeping the place and route of different components of existing logic unchanged and just adding few gates to the design.