DAGAR: an automatic pipelined microarchitecture synthesis system

An automated microarchitecture synthesis system called DAGAR is presented. DAGAR takes as input a behavioral description of a digital system and outputs a microinstruction (MI) sequence and a data path. In microarchitectures synthesized by DAGAR the functional units (FUs) may take one or more clocks (i.e. MIs) to perform an operation. These are called multiclocked FUs. Additionally, if these FUs can accept new data while processing data from a previous MI, they are called pipelined FUs. The use of pipelined FUs is shown to decrease the number of FUs in the data path without a time penalty. Unlike other systems, DAGAR deals with the partitioning of a single FU into stages.<
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